Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. The most common semiconductor technology presently used is silicon-based. One silicon-based semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET is one of the basic building blocks of modern electronic circuits. These electronic circuits realize improved performance and lower costs as the performance of the MOSFET is increased and as manufacturing costs are reduced.
A typical MOSFET device includes a semiconductor substrate on which a gate electrode, such as a polysilicon line, is disposed. The gate electrode, which acts as a conductor, receives an input signal to control operation of the device. Source and drain regions are typically formed in regions of the substrate adjacent the gate electrodes by doping the regions with a dopant of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region. The typical MOSFET is symmetrical, in that the source and drain are interchangeable. Whether a region acts as a source or drain typically depends on the respective applied voltages and the type of device being made. The collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
The semiconductor industry is continually striving to improve the performance of MOSFET devices. The ability to create devices with sub-micron features has allowed significant performance increases, for example, from decreasing performance degrading resistances and parasitic capacitances. The attainment of sub-micron features has been accomplished via advances in several semiconductor fabrication disciplines. For example, the development of more sophisticated exposure cameras in photolithography, as well as the use of more sensitive photoresist materials, have allowed sub-micron features, in photoresist layers, to be routinely achieved. Additionally, the development of more advanced dry etching tools and processes have allowed the sub-micron images in photoresist layers to be successfully transferred to underlying materials used in MOSFET structures.
As the distance between the source region and the drain region of the MOSFET (i.e., the physical channel length) decreases in the effort to increase circuit speed and complexity, the junction depth of source/drain regions must also be reduced to prevent unwanted source/drain-to-substrate junction capacitance. However, obtaining these smaller junction depths tests the capabilities of current processing techniques, such as ion implantation with activation annealing using rapid thermal annealing. Rapid thermal annealing typically involves heating the silicon wafer, after implanting, under high-intensity heat lamps. Implanting or doping amorphitizes the silicon substrate, and the activation annealing is used to recrystallize the amorphitized silicon region.
As a result of the limitations of rapid thermal annealing, laser thermal annealing (LTA): is being implemented, particularly for ultra-shallow junction depths. Laser thermal annealing may be performed after ion implantation of a dopant and involves heating the doped area with a laser. The laser radiation rapidly heats the exposed silicon such that the silicon begins to melt. The diffusivity of dopants into molten silicon is about eight orders of magnitude higher than in solid silicon. Thus, the dopants distribute almost uniformly in the molten silicon and the diffusion stops almost exactly at the liquid/solid interface. The heating of the silicon is followed by a rapid quench to solidify the silicon, and this process allows for non-equilibrium dopant activation in which the concentration of dopants within the silicon is above the solid solubility limit of silicon. Advantageously, this process allows for ultra-shallow source/drain regions that have an electrical resistance about one-tenth the resistance obtainable by conventional rapid thermal annealing.
A problem associated with laser thermal annealing is that the fluence absorbed by the substrate can vary across the wafer, resulting in uneven heat distribution, due to features of varying density, such as gate electrodes, formed on the surface of the wafer. This occurs because the laser heats the wafer on a localized basis and only on the surface, not throughout its bulk. Therefore, material adjacent to the wafer surface has a large impact on the temperature of the irradiated area of the surface. For example, as the density of gate electrodes (i.e., polysilicon lines) formed on a particular area of a wafer increases, the amount of fluence reflected or scattered from that particular area also increases, as compared to an area with a lesser density of polysilicon lines. When the fluence reflected by a particular area increases, the amount of fluence absorbed by that area decreases. The opposite holds true as the density of polysilicon lines in a particular area decreases. Thus, depending upon the density of the polysilicon lines, the substrate heating at given areas disadvantageously varies across the wafer surface.
Accordingly, a need exists for an improved laser anneal process that allows greater uniformity of heating of the substrate surface despite varying feature density across the surface.